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| data sheet august 1999 L8567 slic for peoples republic of china applications features n low active power (typical 149 mw during on-hook transmission) n sleep state for low idle power (47 mw typical) n quiet tip/ring polarity reversal n distortion-free on-hook transmission n C35 v to C65 v battery operation n convenient operating states: forward active polarity reversal active sleep forward disconnect n supervision functions: fixed threshold off-hook detector with longitudinal rejection and hysteresis ring trip detector thermal shutdown indication n adjustable loop current limit n three driver outputs for relay driver n led driver output to indicate off-hook n latched parallel data interface n battery and +5 v required: optional auxiliary lower voltage battery to reduce short loop power n C40 c to +85 c operational temperature range n user-selectable power management techniques n thermal protection n 32-pin plcc or 44-pin plcc packaging description general this electronic subscriber loop interface circuit (slic) is optimized for low cost and low power con- sumption while providing a full-feature set. included in the feature set is quiet reverse battery. quiet polarity reversal is possible because the ac path is uninterrupted during transmission. the dc loop current limit is user-adjustable via a single exter- nal resistor. the maximum battery voltage is speci- fied as C65 v for long loop applications. the L8567 supports on-hook transmission. the total short loop off-hook power may be reduced by use of a lower-voltage auxiliary battery supply. if, when using the 32-pin plcc, the user does not wish to supply an auxiliary battery, the component of the total short loop off-hook power that is dissipated on the L8567 slic is controlled by use of an external power resistor. with the 44-pin plcc, a power resis- tor is not necessary. included are both the loop closure and ring trip supervision functions. the loop closure threshold is fixed internally, which eliminates the need for an external precision resistor to set the threshold. to minimize noise at the supervision output, hysteresis is included on the loop closure function. the loop clo- sure and ring trip outputs are multiplexed into a sin- gle nstat output. also included is a thermal shutdown mechanism. if device temperature exceeds 165 c, as may be the case under an extended power cross fault, the slic will shut down (i.e., enter a high-impedance state) to provide protection against the fault. a logic output will indicate the slic is in thermal shutdown.
2 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for table of contents contents page features ......................................................................1 description...................................................................1 general...................................................................1 application for peoples republic of china ............4 pin information ............................................................6 coding information ......................................................9 absolute maximum ratings.......................................11 recommended operating conditions .......................11 electrical characteristics ...........................................12 logic interface .....................................................14 ring trip requirements .......................................16 test configurations ...................................................17 rfi rejection........................................................19 functional description ...............................................21 general.................................................................21 use with t7507 codec for use in peoples republic of china ..............................................21 chip set performance specifications ........................22 gain......................................................................22 gain flatnessin band .......................................22 gain flatnessout of bandhigh frequencies .......................................................22 gain flatnessout of bandlow frequencies .......................................................22 loss vs. level relative to loss at C10 dbm input at 1020 hz ................................................23 return loss ..........................................................23 hybrid balance .....................................................23 applications ...............................................................24 design considerations .........................................26 characteristic curves ...........................................27 power control.......................................................28 power controlauxiliary battery .........................29 power control32-pin plcc with power control resistor .................................................29 power considerations ..........................................30 power control44-pin plcc package ...............32 dc characteristics ......................................................33 loop range..........................................................34 dc applications ..........................................................34 on-hook transmission.........................................34 supervision...........................................................35 loop closure ........................................................35 ring trip detection...............................................36 other supervision functions ................................36 latched parallel data interface ............................37 ac design .............................................................38 first-generation codecs ......................................38 second-generation codecs .................................38 third-generation codecs .....................................38 t7507 codec........................................................38 outline diagrams.......................................................39 32-pin plcc ........................................................39 44-pin plcc ........................................................40 ordering information..................................................41 figures page figure 1. functional diagram .....................................5 figure 2. 32-pin diagram (plcc chip) ......................6 figure 3. 44-pin diagram (plcc chip) ......................6 figure 4. ring trip circuits .......................................16 figure 5. timing requirements ................................16 figure 6. basic test circuit ......................................17 figure 7. metallic psrr ...........................................18 figure 8. longitudinal psrr ....................................18 figure 9. longitudinal balance .................................18 figure 10. longitudinal impedance ..........................18 figure 11. ac gains ..................................................18 figure 12. rfi rejection test circuit .......................19 figure 13. rfi testing, forward battery, 600 w loop, no capacitor, 1 vrms .........20 figure 14. rfi testing, forward battery, 600 w loop, no capacitor, 2 vrms .........20 figure 15. termination impedance ...........................22 figure 16. transmit and receive direction frequency-dependent loss relative to gain at 3400 hz ..................................22 figure 17. loss vs. level ..........................................23 figure 18. return loss .............................................23 figure 19. hybrid balance ........................................23 figure 20. basic loop start application using t7507 codec and l7583 switch for 200 w + (680 w || 100 nf) complex termination and hybrid balance .............24 figure 21. L8567 typical v cc power supply rejection .................................................27 figure 22. L8567 typical v bat power supply rejection .................................................27 figure 23. L8567 loop current vs. loop voltage .....27 figure 24. L8567 loop/battery current (with battery switch) vs. loop resistance ...................27 figure 25. power derating ........................................28 figure 26. tip/ring voltage decrease .....................33 figure 27. slic 2-wire output stage .......................34 figure 28. ring trip equivalent circuit and equivalent application .............................36 figure 29. simplified control scheme ......................37 figure 30. logic output latches .............................. 38 lucent technologies inc. 3 data sheet august 1999 peoples republic of china applications L8567 slic for table of contents (continued) tables page table 1. pin descriptions .................................................................................................... ....................................7 table 2. input state coding .................................................................................................. ..................................9 table 3. supervision coding .................................................................................................. ...............................10 table 4. power supply ........................................................................................................ ..................................12 table 5. 2-wire port .......................................................................................................... .....................................13 table 6. analog pin characteristics ........................................................................................... ............................13 table 7. ac feed characteristics .............................................................................................. .............................14 table 8. logic inputs (b0, b1, en, rd1i, rd2i, and rd3i) and outputs (nstat and ntsd) ............................14 table 9. drivers (rd1o, rd2o, and rd3o) ....................................................................................... ..................15 table 10. led driver (nled) ................................................................................................... ..............................15 table 11. timing requirements (di, en, do, and rd), cclk = 2.048 mhz ........................................................16 table 12. gain ................................................................................................................ ........................................22 table 13. gain flatnessin band ............................................................................................... ..........................22 table 14. gain flatnessout of bandlow frequencies ........................................................................... ........22 table 15. parts list for loop start application ............................................................................... ........................25 table 16. 200 w + 680 w || 0.1 m f design parameters .........................................................................................26 table 17. power connections ................................................................................................... .............................28 table 18. r pwr = 2600 w .............................................................................................................................. ........31 table 19. r pwr = 2200 w .............................................................................................................................. ........31 table 20. r pwr = 1800 w .............................................................................................................................. ........31 table 21. r pwr = 4400 w .............................................................................................................................. ........32 table 22. r pwr = 2310 w (r pwr = 2200 w + 5%)................................................................................................ 32 table 23. r pwr = 2090 w (r pwr = 2200 w C 5%)................................................................................................ 32 table 24. valid data at nstat and ntsd ........................................................................................ ....................38 4 4 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for description (continued) general (continued) this device uses a latched parallel data input interface and a gated parallel output data interface. level-sensi- tive data latches are used for state control inputs, and level-sensitive control gates are used for supervision outputs. latch and gate control are through an enable pin. when the enable pin is high, input data is latched and the slic will not respond to changes at its logic input. when enable is low, input control data will flow through the latch. valid supervision data will appear at the nstat and ntsd outputs only when enable is low. in this manner, the data input and data output of multiple slics can be serviced by a single control input or output. the L8567 is designed to be controlled/supervised using control/supervision outputs and inputs from the t7507 codec. three relay drivers are also included. these drivers are meant to drive electromechanical relays (emrs). state control of the relay drivers is via latched parallel data inputs. like the b0/b1 and supervision data, control leads from the t7507 codec drive these inputs. the t7507 relay driver control outputs are meant to control the associated control input on all four of the L8567 slics associated with the t7507 codec. if an l7583 solid-state switch is used (instead of emrs), the data control outputs from the t7507 codec will drive the latched state control inputs of the l7583 directly. again, one data control output from the t7507 will drive the corresponding data input on four channels of the l7583. in the case of using the l7583, tie rd1i, rd2i, and rd3i relay driver control inputs of the L8567 to ground. included are two supervision outputs. both supervision outputs are the wire-or of the loop closure and ring trip detectors. one (nstat) is used as a data control output and is gated via the en input. the other (nled) can be used to drive an led to indicate loop states. the nled driver is an open collector output, so multi- ple outputs may be used to drive a single led. nled is not gated, so valid supervision data appears at nled regardless of the state of en. nled can be used as an alternative, nongated, data control output. the L8567 is available in a 32-pin plcc or 44-pin plcc package. application for peoples republic of china this slic may be used with any commercially avail- able codec; however, when used with the lucent tech- nologies microelectronics group t7507, the two devices form a complete line circuit optimized for requirements in the peoples republic of china. the ac interface between the two components is extremely simple, requiring only a single capacitor in the transmit direction and a short-circuit connection, using no exter- nal components, in the receive direction. the complex 200 w + 680 w || 100 nf termination and hybrid balance is digitally synthesized by the t7507 codec. additionally, the tip/ring to pcm (transmit) gain is fixed and set digitally by the t7507 codec at 0 db. the pcm to tip/ring (receive) gain is also digitally set by the t7507 codec and is programmable via a bit in the codec serial data control stream to either C3.5 db or C7.0 db. the control interfaces of the L8567 and t7507 are designed for compatibility with each other. both the t7507 codec and L8567 slic require only battery and +5 v to operate. when both devices are used, no C5 v supply is required. lucent technologies inc. 5 data sheet august 1999 peoples republic of china applications L8567 slic for description (continued) application for peoples republic of china (continued) 12-2551.f (f) * relay driver controls routed to L8567 rd1i, rd2i, and rd3i pins when using emr. if l7583 solid-state switch is used, driver co ntrol buses are routed directly to l7583 control inputs, and slic pins rd1i, rd2i, and rd3i are grounded. figure 1. functional diagram thermal shutdown sense + C C + C + + C a = 1 a = C1 power conditioning & reference cf1 pt pr current limit set i prog rtsn rtsp ring trip detector vtx rcvp rcvn nled rd1o cf2 + + C C tip/ring current sense tg rectifier pwr led drive relay drive relay drive relay drive nlc nrdet ntsd nstat latches logic v dd dgnd rd2o rd3o v cc v bat2 bgnd v bat1 loop closure detector dc out 3 1 rd3i rd2i rd1i b1 b0 en to L8567 1, 2, 3* from t7507 codec from L8567 1, 2, 3 to t7507 codec ntsd nstat agnd 6 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for pin information 12-2548.i (f) figure 2. 32-pin diagram (plcc chip) 5-5779 (f).a figure 3. 44-pin diagram (plcc chip) en ntsd rcvn agnd vtx tg cf2 5 7 8 9 10 11 12 13 14 15 6 43213231 16 18 19 20 17 30 27 26 25 24 23 22 21 28 29 cf1 nled rd1o rd2o dgnd v cc v dd i prog dc out rtsp rcvp bgnd rd3o rd1i rd2i rd3i b0 b1 nstat 32-pin plcc pr pwr v bat2 rtsn pt v bat1 nc rcvp en agnd vtx tg cf2 cf1 nled rd1o rd2o v dd v cc i prog dc out 7 9 10 11 12 13 14 15 16 17 8 6 4 3 2 1 4443424140 5 18 20 21 22 23 24 25 26 27 28 19 39 37 36 35 34 33 32 31 30 29 38 rcvn nc dgnd 44-pin plcc pr nc v bat1 rd2i rd1i nstat nc pwr bgnd rtsn nc nc nc rtsp nc nc pt rd3o b0 b1 rd3i nc ntsd nc nc v bat2 lucent technologies inc. 7 data sheet august 1999 peoples republic of china applications L8567 slic for pin information (continued) table 1. pin descriptions 44-pin 32-pin symbol type description 2 1 rd3i i relay driver 3 input. this latched logic input sets the state of the relay driv- er number 3. when using emrs, the relay driver is controlled by this input via a data bus or independent data line. when using an l758x solid-state switch, the solid-state switch is controlled directly via the data bus or inde- pendent data line and the relay driver is unused; in this case, tie this logic input to ground. 3 2 rd2i i relay driver 2 input. this latched logic input sets the state of the relay driv- er number 2. when using emrs, the relay driver is controlled by this input via a data bus or independent data line. when using an l758x solid-state switch, the solid-state switch is controlled directly via the data bus or inde- pendent data line and the relay driver is unused; in this case, tie this logic input to ground. 4 3 rd1i i relay driver 1 input. this latched logic input sets the state of the relay driv- er number 1. when using emrs, the relay driver is controlled by this input via a data bus or independent data line. when using an l758x solid-state switch, the solid-state switch is controlled directly via the data bus or inde- pendent data line and the relay driver is unused; in this case, tie this logic input to ground. 6 4 rd3o o relay driver 3 output. output to drive an emr, controlled by rd3i. 5, 12, 14, 15, 20, 26, 28, 32, 35, 39, 42, 43 nc no connect. 7 5 rd2o o relay driver 2 output. output to drive an emr, controlled by rd2i. 8 6 rd1o o relay driver 1 output. output to drive an emr, controlled by rd1i. 9 7 nled o nstat led driver. this output is equivalent to nstat, except this output has sufficient drive capability to drive an led. this led driver output is an open-collector output, so multiple outputs may be used to drive a single led. this output may be used as an alternative logic output to the latched nstat output to indicate ring trip or loop supervision status. this output is valid re- gardless of the state of en. 10 8 dgnd pwr digital ground. 11 9 v dd pwr +5 v digital power supply. 13 10 v cc pwr +5 v analog power supply. 16 11 i prog i current-limit program resistor. a resistor to dc out sets the dc current limit. 17 12 dc out o dc output voltage. this output is a voltage that is directly proportional to the absolute value of the differential tip/ring current. 18 13 rtsp i ring trip sense positive. connect this pin to the ring relay and to the ringer series through a high-value resistor. 19 14 rtsn i ring trip sense negative. connect this pin to the ringing generator through a high-value resistor. 8 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for pin information (continued) table 1. pin descriptions (continued) 44-pin 32-pin symbol type description 21 15 pr i/o protected ring. the output of the ring driver amplifier and input to loop sensing circuitry. connect to loop through overcurrent series resistance. 22 16 pt i/o protected tip. the output of the tip driver amplifier and input to loop sensing cir- cuitry. connect to loop through overcurrent series resistance. 23 17 v bat1 pwr battery supply. most negative primary high-voltage power supply. 24 18 bgnd pwr battery ground. ground return for battery supply. 25 19 v bat2 pwr auxiliary battery supply. connect to the lower-voltage (magnitude) auxiliary battery supply. if a lower-voltage auxiliary battery is not used, connect directly to the primary high-voltage battery side. 27 20 pwr pwr power control. with a 32-pin plcc, connect a lower-voltage auxiliary battery supply directly to pwr or connect a resistor from this node to high-voltage bat- tery to control short-loop power dissipation. with a 44-pin plcc, connect the higher-voltage battery directly to pwr. please see the power control section of this data sheet for more information. 29 21 cf1 filter capacitor 1. connect a 0.47 m f capacitor from this pin to cf2. 30 22 cf2 filter capacitor 2. connect a 0.1 m f capacitor from this pin to agnd. 31 23 tg i transmit gain. noninverting input to internal ax transmit amplifier. connect a 7.87 k w resistor from this node to vtx to set internal slic transconductance to 39.75 v/a. transconductance of 39.75 v/a is assumed for use with t7507 codec. 33 24 vtx o transmit ac output voltage. output of slic transmit amplifier. this output is a voltage that is directly proportional to the differential tip/ring current. connect a 7.87 k w resistor from this node to tg to set internal slic transconductance to 39.75 w . 34 25 agnd pwr analog signal ground. 36 26 rcvn i receive ac signal (inverting). this high-impedance input controls the ac differ- ential voltage on tip and ring. 37 27 rcvp i receive ac signal (noninverting). this high-impedance input controls the ac differential voltage on tip and ring. 38 28 en i data enable. level-sensitive data latch control; when high, data at the b0, b1, and relay driver control inputs is latched. when low, the data latch is transparent and control signals will flow through the data latch to the slic control logic. nstat and ntsd supervision outputs are valid only when en is low. 40 29 ntsd o not thermal shutdown. this gated logic output indicates if the L8567 die tem- perature has exceeded the thermal shutdown temperature and the device has entered the thermal shutdown mode. input en needs to be low for valid data to appear at ntsd. the actual thermal shutdown is not affected by en. 41 30 nstat o loop detector output/ring trip output. this gated logic output is a wired-or of the not loop closure/not ring trip detect outputs. when low, this logic output indicates that an off-hook condition exists or that ringing has been tripped. input en needs to be low for valid data to appear at nstat. 44 31 b1 i state control input. this latched logic input, with b0, controls the state of the slic. 1 32 b0 i state control input. this latched logic input, with b1, controls the state of the slic. lucent technologies inc. 9 data sheet august 1999 peoples republic of china applications L8567 slic for coding information table 2 shows the input state coding. table 2. input state coding * all logic inputs are latched. the data latch is controlled by pin en. the en latch control is level sensitive. when en is high, the input data latches are active; that is, data at the b0, b1, rd1i, rd2i, and rd3i inputs are latched. the l atched data will control the state of the slic and drivers so that the slic and drivers will not respond to changes at the logic inputs while th e level at en is high. when en is low, the input latch is not active; therefore, data at the logic inputs will flow through the latch and immedi ately determine the state of the slic and drivers. ? if using an l758x solid-state switch, the switch is controlled directly from the t7507 codec; thus the relay drivers in the l8 567 slic cannot be used. if the relay drivers are not used, force them into the lowest power (not active) state by connecting rd1i, rd2i, and rd3i to ground. b0* b1* rd3i* rd2i* rd1i* state/definition 1 1 x x x powerup, forward battery. normal talk and battery feed state. pin pt is positive with respect to pr. on-hook transmission is enabled. the ring trip and loop closure detectors are active. 1 0 x x x powerup, reverse battery. normal talk and battery feed state. pin pr is positive with respect to pt. on-hook transmission is enabled. the ring trip and loop closure detectors are active. 0 1 x x x low-power scan. except for off-hook supervision, all circuits are shut down to conserve power. pin pt is positive with respect to pr. thermal shutdown is active. note that the ring trip detector is not active during the low-power scan. to ensure that the ring trip detector is active during ring- ing, the L8567 slic must be put into the forward or reverse powerup state before applying power ringing to the loop. 0 0 x x x disconnect. the tip and ring amplifiers are turned off and the slic goes into a high-impedance (>100 k w ) state. the L8567 will reset into this state on powerup. x x 1 x x driver rd1 output is active. input pin rd1i is high. this will activate or place the rd1 driver output into the on state. in the on state, the driver will supply up to 40 ma of current (at 0.6 v) to the coil of an emr, thus acti- vating the emr. x x 0 x x driver rd1 output is not active ? . input pin rd1i is low. this will place the rd1 driver output into the off state. in the off state, the driver will not supply current to the coil of an emr, thus deactivating the emr. x x x 1 x driver rd2 output is active. input pin rd2i is high. this will activate or place the rd2 driver output into the on state. in the on state, the driver will supply up to 40 ma of current (at 0.6 v) to the coil of an emr, thus acti- vating the emr. x x x 0 x driver rd2 output is not active ? . input pin rd2i is low. this will place the rd2 driver output into the off state. in the off state, the driver will not supply current to the coil of an emr, thus deactivating the emr. x x x x 1 driver rd3 output is active. input pin rd3i is high. this will activate or place the rd3 driver output into the on state. in the on state, the driver will supply up to 40 ma of current (at 0.6 v) to the coil of an emr, thus acti- vating the emr. x x x x 0 driver rd3 output is not active ? . input pin rd3i is low. this will place the rd3 driver output into the off state. in the off state, the driver will not supply current to the coil of an emr, thus deactivating the emr. 10 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for coding information (continued) table 3 gives the output coding. table 3. supervision coding * data outputs nstat and ntsd are gated. in order to drive the nstat or ntsd outputs low, both the internal detector (i.e., an o ff-hook or thermal shutdown condition, respectively, exists) and pin en must be low. ? this output is not latched; data is valid regardless of the state of en. it can be used to drive an led or as an alternative u nlatched ring trip/off-hook detector. output state nstat* 0 off-hook or ring trip. dc current greater than the typical 11 ma loop current threshold is flowing in the subscriber loop, or the ring trip comparator has detected a dc voltage greater than the ring trip threshold. this indicates that dc current is flowing in the loop with the ring relay set in the power ring state. the presence of dc current in the power ring state implies that the handset is off-hook, or that a ring trip condition exists. this is a latched output. en must be low for data on this output to be valid. 1 on-hook or not ring trip. dc current less than the difference of the off-hook current threshold and loop current hysteresis is flowing, or the loop is in the power ringing state and the handset is on-hookno dc current has been detected. this is a latched output. en must be low for data on this output to be valid. ntsd* 0 the slic die temperature has exceeded the thermal shutdown temperature threshold, and the slic is forced into the equivalent of the disconnect state, regardless of the state of the b0 and b1 logic inputs. there is a hysteresis in the shutdown circuit, and the device will remain in thermal shutdown until the die temperature drops below the hysteresis threshold. this is a latched output. en must be low for data on this output to be valid. 1 the slic die temperature has not exceeded the thermal shutdown temperature threshold, and the slic state is set per b0 and b1 logic. this is a latched output. en must be low for data on this output to be valid. nled ? 0 identical to the off-hook or ring trip state of output nstat. in this state, nled can supply 10 ma at 1.0 v, which is sufficient to drive an led. this output is an open collector output, so multiple nled outputs from different devices can be used to drive a common led. this output is not latched, so it has valid data regardless of the state of en. nled can be used as an alternative to the latched nstat output. 1 identical to the on-hook or not ring trip state of the pin nstat. lucent technologies inc. 11 data sheet august 1999 peoples republic of china applications L8567 slic for absolute maximum ratings (t a = 25 c) stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. * use of an auxiliary battery, v bat2 , whose magnitude is equal to the primary battery v bat1 but does not exceed the absolute maximum rating, will not damage the chip. however, in a 32-pin plcc, it will drive the L8567 into thermal shutdown under short-loop conditions. use a power resistor to node pwr. note: the ic can be damaged unless all ground connections are applied before, and removed after, all other connections. furtherm ore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. some of the known examples of conditions that cause such potentials during powerup are 1) an inductor connected to tip and ring can force an overvoltage on v bat through the protection devices if the v bat connection chatters, and 2) inductance in the v bat lead could resonate with the v bat filter capacitor to cause a destructive overvoltage. recommended operating conditions parameter symbol min typ max unit +5 v power supply v cc 7.0 v +5 v digital supply v dd 7.0 v battery (talking) supplies * v bat1, v bat2 C70 v logic input voltage C0.5 7.0 v analog input voltage C7.0 7.0 v maximum junction temperature t j 165 c storage temperature range t stg C40 125 c relative humidity range r h 5 95 % ground potential difference (bgnd to agnd) 3 v parameter min typ max unit ambient temperature C40 85 c v cc supply voltage 4.75 5.0 5.25 v v dd supply voltage 4.75 5.0 5.25 v v bat1 supply voltage C65 C48 C35 v v bat2 auxiliary battery supply voltage C35 C24 C15 v dc loop current-limit programming range 15 40 45 ma on- and off-hook 2-wire signal level 3.17 dbm 12 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for electrical characteristics minimum and maximum values are testing requirements in the temperature range of 25 c to 85 c and battery range of C35 v to C65 v. these minimum and maximum values are guaranteed to C40 c based on component simulations and design verification of samples, but devices are not tested to C40 c in production. the test circuit shown in figure 6 is used unless otherwise noted. positive currents flow into the device. typical values are characteristics of the device design at 25 c based on engineering evaluations and are not part of the test requirements. supply values used for typical characterization are v cc = v dd = 5.0 v, v bat1 = C48 v, v bat2 = C25.5 v. table 4. power supply 1. this parameter is not tested in production. it is guaranteed by design and device characterization. 2. this is the total power drawn from the power supplies. if a power resistor is not used, the total power is dissipated by the slic through the package. if a power resistor is used, the power is shared by the resistor and the slic. parameter min typ max unit power supply rejection 500 hz to 3 khz (see figures 6 and 7.) 1 : v cc (1 khz) v bat (500 hz3 khz) 35 45 db db thermal protection shutdown (t tsd ) 1 165 c thermal resistance, junction to ambient ( q ja ) (still air) 1 : 32-pin plcc 44-pin plcc 60 47 c/w c/w power supplypowerup, no loop current with on-hook trans- mission, relay drivers off, dc supplies at typical values, use v bat1 and v bat2 : i cc + i dd i bat1 (v bat1 = C48 v) i bat2 (v bat2 = C24 v) quiescent active power dissipation 6.0 2.25 0.45 149 6.6 2.7 0.54 180 ma ma ma mw power supplylow-power scan, forward battery, no loop cur- rent, relay drivers off, use v bat1 and v bat2 : i cc + i dd i bat1 (v bat1 = C48 v) i bat2 (v bat2 = C24 v) quiescent active power dissipation 4.0 0.61 0.0 47 4.5 0.78 0.0 60 ma ma ma mw power supplypowerup, no loop current with on-hook trans- mission, relay drivers off, dc supplies at typical values, use v bat1 only: i cc + i dd i bat (v bat1 = C48 v) quiescent active power dissipation 2 6.0 2.7 160 6.6 3.46 199 ma ma mw power supplylow-power scan, forward battery, no loop cur- rent, relay drivers off: i cc + i dd i bat (v bat1 = C48 v) power dissipation 2 4.0 0.61 47 4.5 0.78 60 ma ma mw lucent technologies inc. 13 data sheet august 1999 peoples republic of china applications L8567 slic for electrical characteristics (continued) table 5. 2-wire port 1. this parameter is not tested in production. it is guaranteed by design and device characterization. 2. the longitudinal current is independent of dc loop current. 3. current-limit i lim is programmed by a resistor, r prog , from pin i prog to agnd. r prog (k w ) = 1.59 i lim (ma). 4. ieee is a registered trademark of the institute of electrical and electronics engineers, inc. 5. longitudinal balance of circuit card will depend on loop series resistance matching. table 6. analog pin characteristics parameter min typ max unit tip or ring drive current = dc + longitudinal + signal currents 65 ma signal current 1 10 marms longitudinal current capability per wire 1, 2 8.5 15 marms dc loop current limit 3 : r loop = 100 w programmability range accuracy (18 ma < i lim < 45 ma) 15 i lim 45 15 ma ma % powerup open-loop voltage levels: common-mode voltage differential voltage |v bat + 7.8| v bat /2 |v bat + 7.1| |v bat + 6.4| v v disconnect state: pt resistance (v bat < v pt < 0 v) pr resistance (v bat < v pr < 0 v) 1 1 m w m w dc feed resistance (for i loop below current limit) 110 w loop resistance range (3.17 dbm overload into 200 + 680 || 0.1 f): i loop = 18 ma at v bat = C48 v 1800 w longitudinal to metallic balance ieee 4 std. 455 (see figure 9.) 5 : 50 hz to 300 hz 300 hz to 600 hz 600 hz to 3400 hz 38 48 52 db db db metallic to longitudinal balance: 1 khz to 3 khz 38 db parameter min typ max unit differential pt/pr current sense (dc out ) gain (pt/pr to dc out ): forward battery reverse battery C119 119 v/a v/a loop closure detector threshold (on-hook to off-hook at v bat1 = C 48 v) 9 11 13 ma loop closure detector hysteresis: variation 2 0.5 ma ma ring trip comparator: input offset voltage 10 mv rcvn, rcvp: input impedance gain rcvp to pt/pr gain rcvn to pt/pr 100 2 C2 k w 14 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for electrical characteristics (continued) transmit direction is tip/ring to 4-wire. receive direction is 4-wire to tip/ring. table 7. ac feed characteristics 1. this parameter is not tested in production. it is guaranteed by design and device characterization. logic interface table 8. logic inputs (b0, b1, en, rd1i, rd2i, and rd3i) and outputs (nstat and ntsd) 1. unless otherwise specified, all logic voltages are referenced to dgnd. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. parameter min typ max unit total harmonic distortion200 hz to 4 khz 1 : off-hook on-hook 0.3 1.0 % % transmit gain, f = 1020 hz (see figure 11.); pt/pr to vtx transmit gain 38.56 39.75 40.94 v/a receive gain, f = 1020 hz (see figure 11.); rcvp/rcvn to pt/pr receive gain 1.94 2 2.06 2-wire idle-channel noise (200 w + 680 w || 0.1 f termination): psophometric 1 c-message 3 khz flat 1 C77 12 20 dbmp dbrnc dbrn transmit idle-channel noise: psophometric 1 c-message 3 khz flat 1 C77 12 20 dbmp dbrnc dbrn parameter 1 symbol min max unit high-level input voltage v ih 2.4 v ddd v low-level input voltage v il 0 0.8 v input bias current (high and low) i in 50 m a high-level output voltage (i out = C100 m a) v oh v dd C 1.5 v dd v low-level output voltage (i out = 180 m a) v ol 0 0.4 v output short-circuit current (v out = v dd ) i oss 1 35 ma output load capacitance 2 c ol 0 50 pf lucent technologies inc. 15 data sheet august 1999 peoples republic of china applications L8567 slic for electrical characteristics (continued) logic interface (continued) table 9. drivers (rd1o, rd2o, and rd3o) 1 1. the relay drivers operate using the v dd supply. when v dd is first applied to the device, the relay drivers will power up and remain in the off state until the slic is configured via the data interface. 2. unless otherwise specified, all logic voltages are referenced to dgnd . 3. this parameter is not tested in production. it is guaranteed by design and device characterization . table 10. led driver (nled) 1 1. nled is an open collector output, so multiple nled outputs may be used to drive a common led. 2. unless otherwise specified, all logic voltages are referenced to dgnd. 3. this parameter is not tested in production. it is guaranteed by design and device characterization. parameter 2 symbol min max unit off-state output current (v out = v dd ) i off 200 m a on-state output voltage (i out = 40 ma) v on 0 0.60 v on-state output voltage (i out = 20 ma) v on 0 0.40 v clamp diode reverse current (v out = 0) i r 10 m a clamp diode on voltage (i out = 80 ma) v oc v cc + 0.5 v cc + 3.0 v turn-on time 3 t on 10 m s turn-off time 3 t off 10 m s parameter 2 symbol min max unit off-state output current (v out = v dd ) i off 10 m a on-state output voltage (i out = 10 ma) v on 0 1.0 v turn-on time 3 t on 10 m s turn-off time 3 t off 10 m s 16 16 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for electrical characteristics (continued) ring trip requirements n ringing signal: voltage, minimum 35 vrms, maximum 100 vrms. frequency, 17 hz to 28 hz. crest factor, 1.4 to 2. n ringing trip: 100 ms (typical), 250 ms (v bat = C33 v, loop length = 530 w ). n pretrip: the circuits in figure 4 will not cause ringing trip. 5-5841 (f) figure 4. ring trip circuits ring ring ring 100 w 10 k w 8 f tip tip tip 2 m f 200 w switch closes < 12 ms table 11. timing requirements (di, en, do, and rd), cclk = 2.048 mhz 1. unless otherwise specified, all times are measured from the 50% point of logic transitions. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. 5-5808a figure 5. timing requirements symbol parameter 1 min max unit t r , t f input rise and fall time en (10% to 90%) 2 0 75 ns c in maximum input capacitance 2 5 pf t pd01 propagation delay en to do 2 0 977 ns t pdr propagation delay en to rd outputs 2 0 10 m s t sdc minimum setup time from di to en 2 488 ns t hed minimum hold time from en to di 2 488 ns t wen minimum pulse width of en 2 1465 m s twen cclk en nstat/ntsd tsdc rd1, rd2, rd3 csel b0/b1 tpd01 thed lucent technologies inc. 17 data sheet august 1999 peoples republic of china applications L8567 slic for test configurations 12-2578.e (f) figure 6. basic test circuit nstat v bat1 v bat1 bgnd v cc agnd v cc 0.1 m f0.1 m f pt pr i prog dc out rtsp rtsn tg rcvp cf1 vtx rcvn ntsd 0.1 m f cf2 r loop xmt 51.1 k w 11 k w rcv 68 w L8567 slic tip ring 7.87 k w vtx 27.4 k w 0.1 m f pwr 0.1 m f v bat2 b0 en b1 rd1o rd2o rd2i rd3i rd1i rd3o v bat2 68 w 63.4 k w 18 18 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for test configurations (continued) psrr = 20 log 12-2582 (f) figure 7. metallic psrr psrr = 20 log 12-2583 (f) figure 8. longitudinal psrr longitudinal balance = 20 log 12-2584 (f) figure 9. longitudinal balance 12-2585 (f) figure 10. longitudinal impedance 12-2587.h (f) figure 11. ac gains v s 4.7 m f 100 w v bat or v cc disconnect v t/r 900 w v bat or v cc pt pr basic test circuit + C capacitor bypass v s v t/r --------- - v s 4.7 m f 100 w v bat or v cc disconnect bypass 56.3 w v bat or v cc pt pr basic test circuit 67.5 w 10 m f 10 m f 67.5 w v m + C capacitor v s v m ------ - pt pr basic test circuit 365 w 100 m f 100 m f 365 w v m + C v s v s v m ------ - pt pr basic test circuit + C + C i long i long v pt v pr z long = or d v pt d i long d v pr d i long pt pr basic test circuit 680 w v t/r + C g xmt = v xmt v t/r g rcv = v t/r v rcv xmt rcv v s r g = 7.87 k w 200 w 0.1 m f tg vtx rcv lucent technologies inc. 19 data sheet august 1999 peoples republic of china applications L8567 slic for test configurations (continued) rfi rejection figures 1214 show the typical rfi rejection performance of the L8567 under the various conditions listed within each figure title. the test circuit is shown below. the input signal is 100 khz to 100 mhz, 1 vrms and 2 vrms, 80% am, with 1 khz side tone applied using an r&s t network (cdn). this test is performed to the iec 801-6 (1994) specification. note that all power supplies (v cc , v dd , v bat ) are bypassed to ground, as close as possible to the ic, with 1 nf capacitors, and all grounds are shorted on the bottom of the board as close as possible to the ic. note that no rfi lp filter is used at tip and ring. 12-3456 (f) * hp is a registered trademark of hewlett-packard company. figure 12. rfi rejection test circuit hp * tims 4935a r&st network 600 w L8567 hp 3580a spectrum analyzer 1 k w hp 8648c signal generator ring tip vtx 20 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for test configurations (continued) rfi rejection (continued) 12-3471a (f) figure 13. rfi testing, forward battery, 600 w w w w loop, no capacitor, 1 vrms 12-3472a (f) figure 14. rfi testing, forward battery, 600 w w w w loop, no capacitor, 2 vrms 0102030405060708090100 C110 C100 C90 C80 C70 C60 C50 frequency in mhz 600 w termination (dbm) 600 w termination (dbm) 0 10 2030 4050 607080 90100 C110 C100 C90 C80 C70 C60 C50 frequency in mhz lucent technologies inc. 21 data sheet august 1999 peoples republic of china applications L8567 slic for functional description general the L8567 is a full-feature subscriber loop interface cir- cuit (slic) designed to provide the battery feed and supervision functions to the tip/ring pair. the device uses a current sense/voltage feed architecture. that is, the device senses tip/ring current and supplies a pre- cise voltage that is proportional to the tip/ring current at the vtx output. the overall transconductance (tip/ring current to vtx voltage gain) is set by a single external resistor, r tg . the voltage at vtx is fed to the codec. the device feeds a precise differential voltage to tip and ring as a function of the signal voltages at the rcvn and rcvp inputs. the codec output is con- nected to the rcvn/rcvp slic inputs. use with t7507 codec for use in peoples republic of china the L8567 slic and lucent t7507 codec together form a matched device set designed to meet the spe- cific mpt (ministry of post and telecom) requirements for telephony in the peoples republic of china. the ac interface between the L8567 and the t7507 codec is extremely simple, requiring only a single dc blocking capacitor in the transmit direction, and a short-circuit connection between the codec and slic inputs rcvn and rcvp. the t7507 codec has a fixed digital transmit gain stage and two digital gain stages in the receive direction. the choice of gain in the receive direction is user-selectable via a bit in the serial logic input bit stream. the transmit gain of the t7507 codec is such that when the tip/ring to vtx transconductance of the L8567 slic is set to 39.75 v/a (r tg = 7.87 k w ), the overall tip/ring to pcm transmit gain is 0 db into 813 w . (note that 813 w is the equivalent resistance of the prc complex impedance network of 200 w + 680 w || 100 nf at 1000 hz.) the receive gains of the t7507 codec are such that the overall pcm to tip/ring receive gain is user-selectable to either C3.5 db or C7.0 db into 813 w . note also that the t7507 codec will digitally synthesize a termination impedance of 200 w + 680 w || 100 nf. in order to do this, the codec will assume use of 50 w series protection resistors, plus the resistance of the l758x lucent solid-state switch on both tip and ring. if the l758x switch is not used, the return loss perfor- mance will degrade slightly; however, it will still meet mpt standards. gain flatness will not be affected; how- ever, gain levels will shift less than 0.2 db. to compen- sate (if desired), the resistance of the series protection resistor should be increased approximately 20 w , to account for the resistance of the switch. hybrid cancellation is also done digitally by the t7507 codec, assuming a complex hybrid balance network of 200 w + 680 w || 100 nf. the t7507 codec operates off of a single 5 v power supply. thus, a line card using the L8567 slic and t7507 codec does not require a C5 v supply. since the t7507 is a 5 v only device, the analog input and output of the t7507 is referenced to 2.5 v. however, the dynamic input range of the L8567 slic is high enough to accommodate ac signals referenced to 2.5 v, thus eliminating the need for an external dc blocking capaci- tor in the receive direction. the basic loop start sche- matic, using an L8567 slic, t7507 codec, and l7583 switch, for prc termination, is shown in figure 20. the control logic interface of the L8567 slic is matched to the control logic of the t7507. the latched control inputs of the L8567 are designed to be driven by the t7507 control data outputs. the gated supervi- sion outputs of the L8567 slic are designed to feed data inputs to the t7507 codec. the t7507 codec sup- plies the required en pulses to the L8567 slic. con- trol data to the L8567 and supervision from the L8567 is received from, and passed to, the microcontroller at the serial data interface in the t7507 codec. see the t7507 data sheet for additional details. 22 22 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for chip set performance specifications when using the t7507 codec, L8567 slic, l7583 solid-state switch, and 50 w protection resistors, the following line card requirements are achieved; specified termination impedance is shown in figure 15. 5-5324.a figure 15. termination impedance gain * C3.5 or C7.0 gain mode programmable via the t7507 serial data interface. gain flatnessin band gain flatnessout of bandhigh frequencies the transmit and receive directions frequency-depen- dent loss relative to gain at 3400 hz is shown below. this specification is met by using the t7507 codec, L8567 slic, l7583 solid-state switch, and 50 w pro- tection resistors (200 w + 680 w || 0.1 m f termination). 5-5340 figure 16. transmit and receive direction frequency-dependent loss relative to gain at 3400 hz the loss for frequencies 3400 hz < f < 4600 hz is given by: b = 12.5 gain flatnessout of bandlow frequencies table 14. gain flatnessout of bandlow frequencies transmit direction only, loss relative to 1020 hz. this specification is met by using the t7507 codec, L8567 slic, l7583 solid-state switch, and 50 w protection resistors (200 w + 680 w || 0.1 m f termination). table 12. gain gain @ 1020 hz min typ max unit transmit C0.7 0 +0.3 db receive* C4.2 C3.5 C3.2 db receive* C7.7 C7.0 C6.7 db table 13. gain flatnessin band the in-band frequency-dependent loss relative to gain at frequency = 1020 hz, for the transmit and receive directions. this specification is met by using the t7507 codec, L8567 slic, l7583 solid-state switch, and 50 w protection resistors (200 w + 6800 w || 0.1 m f termina- tion). frequency (hz) min max unit 300400 C0.3 1.00 db 400600 C0.3 0.75 db 6002400 C0.3 0.35 db 24003000 C0.3 0.55 db 30003400 C0.3 1.50 db 680 w 0.1 m f 200 w frequency (hz) min loss (db) 16.67 30 40 26 50 30 60 30 0 C5 10 12.5 20 25 30 loss (db) 3400 4000 4600 5000 acceptable region frequency (hz) 1 p 4000 f C () 1200 ----------------------------- sin C db lucent technologies inc. 23 data sheet august 1999 peoples republic of china applications L8567 slic for chip set performance specifications (continued) loss vs. level relative to loss at C10 dbm input at 1020 hz this specification is met by using the t7507 codec, L8567 slic, l7583 solid-state switch, and 50 w pro- tection resistors (200 w + 680 w || 0.1 m f termination). 5-5341 figure 17. loss vs. level return loss the following template is achieved. 5-5325 figure 18. return loss hybrid balance the following template is achieved. 5-5326 figure 19. hybrid balance +3 dbm0 C10 C40 C50 C55 1.6 0.6 0.3 0 C0.3 C0.6 C1.6 loss (db) 18 rl (db) 14 300 500 2000 3400 frequency (hz) 20 tbrl (db) 16 300 500 2500 3400 frequency (hz) 24 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for applications 12-3366a (f) figure 20. basic loop start application using t7507 codec and l7583 switch for 200 w + (680 w || 100 nf) complex termination and hybrid balance r prog 63.4 k w pwr dc out i prog to test bus tring tline t bat crowbar protector tip ring crowbar protector r pt 50 w r pr 50 w rring pr pt rtsp r tsp 2.0 m w c rts2 0.27 m f c rts1 0.022 m f r ts1 402 w r ts2 274 k w r tsn 2.0 m w v bat v ring 0.1 m f c bat1 bgnd v bat1 0.1 m f c dd dgnd v dd 0.1 m f c cc v cc agnd agnd cf1 cf2 c f1 0.47 m f 0.1 m f c f2 ntsd nstat b1 b0 0.1 m f c dd v dd agnd di cclk csel mclk timing and control ifs fsep sync d r d x pcm highway rcvn rcvp vtx 0.1 m f cb2 r tg 7.87 k w tg L8567 slic 1/4 t7507 codec fgnd r bat l7583 switch rtsn v bat2 vf r on vf r op vf x in tsd in testout inring in testin latch v bat2 rd1i rd2i rd3i do to L8567 en0 en1 en2 en3 b0 c b1 c nstat c ntsd c rd1 c rd2 c rd3 c ntsd0 en slic and l7583 switch 1, 2, or 3 to L8567 slic 1, 2, and 3 from L8567 slic 1, 2, and 3 to l7583b 1, 2, and 3 dxen c bat2 0.1 m f ntsd13 from l7583b 1, 2, and 3 lucent technologies inc. 25 data sheet august 1999 peoples republic of china applications L8567 slic for applications (continued) table 15. parts list for loop start application name value function integrated circuits slic L8567 subscriber loop interface circuit (slic). protector crowbar protector 1 1. contact your lucent technologies account representative for protector recommendations. choice of this (and all) component(s ) should be evaluated and confirmed by the customer prior to use in any field or laboratory system. lucent does not recommend use of this p art in the field without performance verification by the customer. this device is suggested by lucent for customer evaluation. the decisio n to use a component should be based solely on customer evaluation. secondary protection. ringing and test access l7583b switches ringing signals and test buses. codec t7507 transmit/receive gains, termination impedance, hybrid balance, d/a, a/d, and filtering. overvoltage protection r pt 50 w protection resistor. ptc or fusible. r pr 50 w protection resistor. ptc or fusible. power supply c bat1 /c bat2 0.1 m f, 20%, 100 v v bat filter capacitors. c cc 0.1 m f, 20%, 10 v v cc filter. c dd 0.1 m f, 20%, 10 v v dd filter. c f1 0.47 m f, 20%, 100 v with c f2 , improves idle-channel noise. c f2 0.1 m f, 20%, 100 v with c f1 , improves idle-channel noise. dc profile r prog 63.4 k w , 1%, 1/16 w sets dc loop current limit. r pwr (with single battery supply) 2.2 k w , 5%, 2 w limits power dissipated on the slic, provides dc power to the loop. ac characteristics c b2 0.1 m f, 20%, 100 v ac/dc separation capacitor. r tg 7.87 k w , 1%, 1/16 w sets slic transconductance. supervision r ts1 402 w , 5%, 2 w ringing source series resistor. r ts2 274 k w , 1%, 1/16 w with c rts2 , forms first pole of a double pole, 2 hz ring trip sense filter. c rts1 0.022 m f, 20%, 5 v with r tsn , r tsp , forms second 2 hz filter pole. c rts2 0.27 m f, 20%, 100 v with r ts2 , forms first 2 hz filter pole. r tsn 2 m w , 1%, 1/16 w with c rts1 , r tsp , forms second 2 hz filter pole. r tsp 2 m w , 1%, 1/16 w with c rts1 , r tsn , forms second 2 hz filter pole. 26 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for applications (continued) design considerations table 16 shows the design parameters of the application circuit shown in figure 20. components that are adjusted to program these values are also shown. table 16. 200 w w w w + 680 w w w w || 0.1 m m m m f design parameters design parameter parameter value components adjusted loop closure threshold 11 ma dc loop current limit 40 ma r prog dc feed resistance 246 w r pt , r pr , l7583 2-wire signal overload level 3.17 dbm ac termination impedance 200 w + 680 w || 0.1 m f set via t7507 hybrid balance line impedance 200 w + 680 w || 0.1 m f set via t7507 transmit gain 0 db set via t7507 receive gain C3.5 db/C7.0 db set via t7507 lucent technologies inc. 27 data sheet august 1999 peoples republic of china applications L8567 slic for applications (continued) characteristic curves 12-2830 (f) figure 21. L8567 typical v cc power supply rejection 12-2871 (f) figure 22. L8567 typical v bat power supply rejection 12-3050.g (f) v bat1 = v bat2 = C48 v. i lim = 40 ma (r prog = 66.5 k w ). figure 23. L8567 loop current vs. loop voltage 12-3470 (f) figure 24. L8567 loop/battery current (with battery switch) vs. loop resistance 10 100 10 5 10 6 C80 C70 C20 C10 0 frequency (hz) 1000 10 4 C50 C40 C60 C30 psrr (db) current limit below current limit 10 100 10 5 10 6 C80 C70 C20 C10 0 frequency (hz) 1000 10 4 C50 C40 C60 C30 psrr (db) below current limit current limit loop current (ma) 0 510 25 0 20 30 40 50 loop voltage (v) 15 20 10 1 r dc 30 45 35 40 1 10 k w 0 200 0.000 0.004 0.010 r loop ( w ) 400 battery/loop output (ma) 600 1000 800 0.016 i loopdc i bat1 i bat2 0.002 0.006 0.012 0.018 0.008 0.014 0.020 0.022 0.024 0.026 0.028 0.030 28 28 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for applications (continued) characteristic curves (continued) 12-2825.b (f) note: curve is relevant only to portion of total power dissipation that is actually dissipated on the slic. figure 25. power derating power control the total power drawn from the talk battery during an off-hook state is the product of the battery voltage times the total dc loop current, plus the slic quiescent power dissipation. note that during the on-hook state, the power is simply the slic quiescent power. p total(off-hook) = v bat i loop + p slic(quiescent) a portion of the total power is dissipated in the sub- scriber loop, and a portion of the total power is dissi- pated in the slic itself. the loop power is used to drive the handset and is given by: p loop = i 2 loop r loop i loop is the dc loop current. in the short dc loops, the dc loop current will be limited by the slic. in the case of the L8567 slic, the dc loop current is determined by external resistor r prog . r loop is the sum of the actual loop resistance (wire resistance and dc handset resis- tance) plus any protection or other series resistance. the active or off-hook power dissipated in the slic is simply the difference of the total power drawn from the talk battery, less the loop power, less the slic quies- cent or on-hook power. p slic(active) = p total C p loop C p slic(on-hook) if the active power dissipated in the slic is too high, the slic temperature will rise above the thermal shut- down threshold and the slic will be driven into a ther- mal shutdown state. the worst case is under short dc loops at elevated ambient temperatures. the power dissipated on the slic must be controlled to avoid forc- ing the slic into thermal shutdown during an active phone conversation. with the L8567 slic, short-loop power dissipation may be controlled using several user-selectable techniques. the first involves use of a lower-voltage auxiliary bat- tery. this will reduce the total short-loop off-hook power. this has the advantage of not only controlling the slic temperature rise, but also minimizing total power drawn from the talk battery. if the user chooses not to provide an auxiliary battery, the power dissipated by the slic must be controlled in some other manner. with the L8567 slic, this may be done in two ways. one technique involves the use of a single external power control resistor. this technique does not minimize total power dissipation; rather it con- trols the power that it is dissipating through the slic package by removing some power from the slic through the resistor, thus avoiding excess temperature rise. because of the higher thermal impedance associ- ated with the 32-pin plcc, this technique may be nec- essary with the 32-pin plcc package option. the other technique is simply to choose the 44-pin plcc package option. the thermal resistance of the 44-pin plcc is low enough to ensure, under most con- ditions, that the thermal shutdown temperature of the slic is not exceeded. power dissipation calculations should be made to assess design margin. for the three configurations discussed above, connec- tions to the v bat1 , v bat2 , and pwr nodes are outlined in the table below. table 17. power connections ambient temperature, t a ( c) 20 40 60 140 180 0 500 1000 1500 2000 80 100 120 160 power (mw) 32 plcc still air 47 c/w 44 plcc option connections to power mode v bat1 v bat2 pwr 32 plcc with auxil- iary battery v bat1 v bat2 v bat2 32 plcc with high- voltage battery and power resistor v bat1 v bat1 v bat1 through power control resistor 44 plcc with high- voltage battery v bat1 v bat1 v bat1 lucent technologies inc. 29 data sheet august 1999 peoples republic of china applications L8567 slic for applications (continued) power controlauxiliary battery with the auxiliary battery technique under long loops, the entire L8567 draws power from the higher-voltage battery. as the loop length decreases and the loop current increases or limits, the final output drive stage of the L8567 slic will draw power from the lower- voltage auxiliary battery. thus, for a given loop, with a given loop current requirement, the minimum battery voltage is used by the L8567 slic, which minimizes the total power consumed. during on-hook or open- circuit conditions, the high battery is seen at tip and ring. all circuits on the L8567, other than the final output drive stage, are powered by the higher-voltage battery regardless of dc loop length. thus, slic quiescent power will be determined solely by the high-voltage battery and will not be reduced under short dc loops. tip/ring voltage varies as a function of loop length, decreasing with decreasing loop length. the battery transition will occur when the tip/ring voltage is less than v bat2 by a diode drop and a v ce(sat) , or about 1 v. thus, the transition point from v bat1 to v bat2 may be controlled by the choice of v bat2 . the relationship is given below: v bat2 = t oh + r dc(tip) * i loop + 2 * r prot * i loop + r loop * i lim + r dc(ring) * i lim + (v diode + v ce(sat) ) where: v bat2 = magnitude of auxiliary battery. t oh = overhead voltage tip to ground, typically 2.5 v. r dc(tip) = dc feed resistance on tip, typically 55 w . i loop = loop current. v bat2 will switch under short-loop conditions where it is likely that the slic will be current limiting; thus, i loop = i lim . r prot = series protection resistance plus l758x resis- tance, nominal 68 w . r loop = loop resistance for transition from v bat1 to v bat2 . i lim = slic current limit set per resistor r lim . r dc(ring) = dc feed resistance on ring, typically 55 w . (v diode + v ce(sat) ) = internal voltage drop associated with battery switch circuit, typically 1 v. thus, the equation may be rewritten: v bat2 = 2.5 v + 55 i lim + 132 i lim + r loop i lim + 55 i lim + 1 v r loop = C 242 w thus, for example, for a nominal loop transition at 700 w , with a 25 ma current limit, v bat2 should be nom- inal 27 v. power control32-pin plcc with power control resistor this section is applicable if the user chooses to use a single high-voltage battery with an external power con- trol resistor. the power resistor is used in conjunction with the 32-pin plcc package. resistor r pwr is connected from pin pwr to the bat- tery supply. this resistor limits the power that is dissi- pated on the slic. dc loop current is shared between the slic and r pwr , thus controlling the actual power that is dissipated on the slic. the value and power rat- ing of r pwr is determined by the thermal capabilities of the L8567s 32-pin plcc package. the value and power rating of r pwr is calculated as shown below. the relationship for the power dissipated in the slic is given by: p slic = p total + p q C p prot C p pwr C p loop (1) where: p slic = the power dissipated in the slic. p total = the total off-hook power dissipation. p q = the slic quiescent or on-hook power dissipation. p prot = the power dissipated in the protection resistors (and l758x switch). p pwr = the power dissipated in r pwr . p loop = the power dissipated in the subscriber loop. the relationships for the individual power dissipation components are: p total = i loop |v bat |(2) p q is the active state open loop power dissipation of the L8567 slic and is specified in table 4 on page 12. p prot = (i loop ) 2 2r p (3) p pwr = (4) p loop = v loop i loop (5) where: i loop is the maximum dc loop current which is the dc loop current limit that is set by resistor r prog . r p is the value of the protection resistor plus the resis- tance of the l758x switch. |v bat | is the magnitude of the maximum battery volt- age. v roh is the overhead voltage associated with the ring lead. v loop is the ring/tip loop voltage. this voltage is a func- tion of the dc loop length or resistance. it will decrease with decreasing loop resistance. r pwr is the resistance of the external resistor r pwr . v bat2 3.5 C i lim -------------------------------- v bat v roh C v loop C () 2 r pwr () ------------------------------------------------------------------------- - 30 30 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for applications (continued) power control32-pin plcc with power control resistor (continued) the maximum power that may be dissipated in the slic , p slic(max) is given by t tsd C t a = t rise (6) (7) where: t tsd is the thermal protection shutdown temperature and is specified in table 4. t a is the maximum ambient operating temperature. t rise is the maximum allowed slic temperature rise to avoid driving the slic into thermal shutdown. p slic(max) is the maximum allowed power that is dissi- pated on the slic to avoid driving the slic into ther- mal shutdown. is the thermal resistance, junction to ambient of the 32-pin plcc package; it is specified in table 4 on page 12. the approach to choosing the value and rating of r pwr follows. first use equations 6 and 7 to determine the maximum allowed power that may be dissipated on the slic without driving the slic into thermal shutdown. next consider equations 1 and 4. in both equation 1 and 4, pick a value of r pwr and for this value, or r pwr , vary v loop from the open-circuit (on-hook) state volt- age to the voltage seen at the minimum expected dc loop length (100 w ). the idea is to use the slic power dissipation value from equation 1, p slic , to ensure that the maximum slic power dissipation value from equa- tion 7, p slic(max) , is not exceeded for any value of loop length. at the same time, using equation 4, try to mini- mize the power dissipated in r pwr so as to choose the minimum power rating of the resistor to minimize cost associated with this resistor. this technique is illus- trated in the following design example. power considerations r pwr design example: assume i loop = 45 ma. this assumes that a 40 ma current limit is programmed by resistor r prog set at 63.4 k w , plus a worst-case 15% tolerance that is speci- fied in table 5. |v bat | = 56 v. 2r p = 136 w . this assumes use of 50 w ptc in both the tip and ring lead associated with the l7583 on resistance. v roh = 4 v (typical). p q = 165 mw as nominally specified in table 4. t tsd = 165 c per table 4. t a = 85 c. = 60 c/w per table 4. v loop is varied from the open-circuit voltage of approx- imately 50 v to the voltage at a 100 w loop length, approximately 5 v. first, using equations 6 and 7, calculate the maximum allowed power dissipation in the slic. t tsd C t a = t rise (6) 165 c C 85 c = 80 c (7) p slic(max) = = 1.33 w given the choice of r pwr chosen, the value of p slic in equation 8 must be less than 1.33 w for all loop lengths (all values of v loop in equation 1). at the same time, r pwr should be chosen to minimize p prw from equa- tion 4. inserting values into equation 1: p slic p total + p q C p prot C p pwr C p loop (8) from equation 2, 3, 4, 5 p slic i loop |v bat | + p q C (i loop ) 2 2r p C C v loop i loop inserting values: 1.33 w < (0.045)(56) + 0.165 w C [(0.045) 2 2(50 + 18)] C C (v loop )(0.045 ma) (9) p slic max () t rise q ja --------------- - = q ja q ja p slic max () t rise q ja --------------- - = 80 c 60 c ---------------- - v bat v roh C v loop C () 2 r pwr -------------------------------------------------------------------------- 56 4 C v loop C () 2 r pwr ------------------------------------------------------ lucent technologies inc. 31 data sheet august 1999 peoples republic of china applications L8567 slic for applications (continued) power considerations (continued) inserting values into equation 4: p pwr = p pwr = (10) at this point, the idea is to choose a value of r pwr , and vary v loop from the on-hook value of approximately 50 v to the very short loop (~100 w ) value of 5 v in both equations 9 and 10. for the choice of r pwr , the relationship in equation 9 must be met to ensure that sufficient power is dissipated in r pwr to ensure that L8567 slic is not driven into thermal shutdown. at the same time, for the choice of r pwr , equation 10 will tell what the power rating of r pwr needs to be. obviously, it is desirable to minimize p prw in equation 10 to minimize the cost associated with component r pwr . an easy way to vary v loop for various values of r pwr is to use a computer-based spreadsheet program. table 18 shows a spreadsheet for the choice of r pwr = 2600 w . as shown, for this choice of resistor under short loop conditions, the power dissipated in the slic exceeds 1.33 w; thus, the slic may be driven into thermal shutdown. therefore, 2600 w is not an appro- priate choice of r pwr . in table 19, r pwr was reduced to 2200 w . as shown in this spreadsheet, under no loop conditions does the slic power dissipation exceed 1.33 w. thus, in terms of slic power dissipation, 2200 w is an appropriate choice. looking at the power dissipated in resistor r pwr , the maximum power dissipation is 0.96 w, which says a rating of 2 w (with margin) is appropriate for 2200 w . in table 20, r pwr was further reduced to 1800 w . again, with this choice, the slic power does not exceed 1.33 w, so in terms of slic power dissipation, 1800 w is also an appropriate choice. however, with 1800 w , the power dissipated in r pwr under short loop conditions exceeds 1 w, which suggests that for 1800 w , the power rating of r pwr should be greater than 2 w. thus, while 1800 w ensures the slic will not be driven into thermal shutdown, because of the higher power rating required compared to 2200 w , 2200 w is a better choice. in table 21, r pwr was increased to 4400 w . this is the minimum value to get the power rating of r pwr to a 0.5 w resistor. however, with this choice of resistor, the slic power will exceed 1.33 w; thus, 4400 w is not appropriate. this result suggests that the minimum power rating of r pwr under the assumed conditions is 1 w. table 22 and table 23 show results for 2200 w with a + 5% and C5% variation, respectively. these tables sug- gest that a 5% tolerance is adequate for r pwr . table 18. r pwr = 2600 w table 19. r pwr = 2200 w table 20. r pwr = 1800 w v bat v roh C v loop C () 2 r pwr -------------------------------------------------------------------------- 56 4 C v loop C () 2 r pwr ------------------------------------------------------ - p slic (w) v loop (v) r pwr ( w ) p pwr (w) 1.334985 5 2600 0.849615 1.281138 10 2600 0.678462 1.208062 15 2600 0.526538 1.115754 20 2600 0.393846 1.004215 25 2600 0.280385 0.873446 30 2600 0.186154 0.723446 35 2600 0.111154 0.554215 40 2600 0.055385 0.365754 45 2600 0.018846 0.158062 50 2600 0.001538 p slic (w) v loop (v) r pwr ( w ) p pwr (w) 1.180509 5 2200 1.004091 1.157782 10 2200 0.801818 1.112327 15 2200 0.622273 1.044145 20 2200 0.465455 0.953236 25 2200 0.331364 0.8396 30 2200 0.22 0.703236 35 2200 0.131364 0.544145 40 2200 0.065455 0.362327 45 2200 0.022273 0.157782 50 2200 0.001818 p slic (w) v loop (v) r pwr ( w ) p pwr (w) 0.957378 5 1800 1.227222 0.9796 10 1800 0.98 0.974044 15 1800 0.760556 0.940711 20 1800 0.568889 0.8796 25 1800 0.405 0.790711 30 1800 0.268889 0.674044 35 1800 0.160556 0.5296 40 1800 0.08 0.357378 45 1800 0.027222 0.157378 50 1800 0.002222 32 32 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for applications (continued) power considerations (continued) table 21. r pwr = 4400 w table 22. r pwr = 2310 w (r pwr = 2200 w + 5%) table 23. r pwr = 2090 w (r pwr = 2200 w C 5%) power control44-pin plcc package with the 44-pin plcc, the thermal impedance of the package is probably enough to ensure the slic ther- mal shutdown temperature is not exceeded. power cal- culations, as illustrated below, should be made to ensure design margin. the still-air thermal resistance of the 44-pin plcc is 47 c/w; however, this number implies zero airflow as if the L8567 were totally enclosed in a box. a more realis- tic number would be 43 c/w. this is an experimental number that represents a thermal impedance with no forced airflow (i.e., from a muffin fan), but from the nat- ural airflow as seen in a typical switch cabinet. the slic will enter the thermal shutdown state at typi- cally 165 c. the thermal shutdown design should ensure that the slic temperature does not reach 165 c under normal operating conditions. assume a maximum ambient operating temperature of 85 c, a maximum current limit of 45 ma, and a maxi- mum battery of C52 v. further, assume a (worst case) minimum dc loop of 100 w and that 100 w protection resistors are used at both tip and ring. 1. t tsd C t a(max) = allowed thermal rise. 165 c C 85 c = 80 c 2. allowed thermal rise = package thermal impedance ? slic power dissipation. 80 c = 43 c/w ? slic power dissipation slic power dissipation (p d ) = 1.9 w thus, if the total power dissipated in the slic is less than 1.9 w, it will not enter the thermal shutdown state. total slic power is calculated as: to t a l p d = maximum battery ? maximum current limit + slic quiescent power. for the L8567, slic quiescent power (p q ) is approxi- mated at 0.167 w. thus, to t a l p d = (C52 v ? 45 ma) + 0.167 w to t a l p d = 2.34 w + 0.167 w to t a l p d = 2.507 w the power dissipated in the slic is the total power dis- sipation less the power that is dissipated in the loop. slic p d = total power C loop power loop power = (i lim ) 2 ? (r dcloop min + 2r p ) loop power = (45 ma) 2 ? (100 w + 200 w ) loop power = 0.61 w slic power = 2.507 w C 0.61 w slic power = 1.897 w < 1.9 w thus, in this example, the thermal design ensures that the slic will not enter the thermal shutdown state. p slic (w) v loop (v) r pwr ( w ) p pwr (w) 1.682555 5 4400 0.502045 1.558691 10 4400 0.400909 1.423464 15 4400 0.311136 1.276873 20 4400 0.232727 1.118918 25 4400 0.165682 0.9496 30 4400 0.11 0.768918 35 4400 0.065682 0.576873 40 4400 0.032727 0.373464 45 4400 0.011136 0.158691 50 4400 0.000909 p slic (w) v loop (v) r pwr ( w ) p pwr (w) 1.228323 5 2310 0.956277 1.195964 10 2310 0.763636 1.141959 15 2310 0.592641 1.06631 20 2310 0.44329 0.969016 25 2310 0.315584 0.850076 30 2310 0.209524 0.709492 35 2310 0.125108 0.547262 40 2310 0.062338 0.363388 45 2310 0.021212 0.157868 50 2310 0.001732 p slic (w) v loop (v) r pwr ( w ) p pwr (w) 1.127662 5 2090 1.056938 1.115581 10 2090 0.844019 1.079576 15 2090 0.655024 1.019648 20 2090 0.489952 0.935796 25 2090 0.348804 0.828021 30 2090 0.231579 0.696322 35 2090 0.138278 0.5407 40 2090 0.0689 0.361155 45 2090 0.023445 0.157686 50 2090 0.001914 lucent technologies inc. 33 data sheet august 1999 peoples republic of china applications L8567 slic for dc characteristics the L8567 slic operates in a dc unbalanced mode. in the forward active state, under open-circuit (on-hook) conditions, the tip to ring voltage will be a nominal 7.1 v less than the battery. this is the overhead volt- age. the tip and ring overhead is achieved by biasing ring a nominal 4.6 v above battery and by biasing tip a nominal 2.5 v below ground. during off-hook conditions, some dc resistance will be applied to the subscriber loop as a function of the phys- ical loop length, protection, and telephone handset. as the dc resistance decreases from infinity (on-hook) to some finite value (off-hook), the tip to ring voltage will decrease as shown below. 12-3431 (f) figure 26. tip/ring voltage decrease as illustrated above, as loop length decreases, the tip to ground voltage will decrease with a slope corre- sponding to one-half the internal dc feed resistance of the slic. (the L8567 dc feed resistance is a nominal 110 w .) the ring to ground voltage will also decrease with a slope corresponding to one-half the internal dc feed resistance of the slic, until the slic reaches the current-limit region of operation. at that point, the slope of the ring to ground voltage will increase to the sum of one-half the internal dc feed resistance of the slic plus approximately 10 k w , which is the slope of the i/v characteristic in the current-limit region. the dc feed characteristic can be described by: v t/r = where: i l = dc loop current. v t/r = dc loop voltage. |v bat | = battery voltage magnitude. v oh = overhead voltage. this is the difference between the battery voltage and the open loop tip/ring voltage. r l = loop resistance, not including protection resistors. r p = protection resistor value. r dc = slic internal dc feed resistance. the design begins by drawing the desired dc template. refer to figures 23, 24, and 26. starting from the on-hook condition and going through to a short circuit, the curve passes through two regions: region 1; on-hook and low loop currents: the slope corresponds to the dc resistance of the slic, r dc1 (plus any series resistance). the open-circuit voltage is the battery voltage less the overhead voltage of the device, v oh (7.0 v typical). region 2; current limit: the dc current is limited to a val- ue determined by external resistor r prog . this region of the dc template has a high resistance (10 k w ). calculate the external resistor as follows: r prog (k w ) = 1.59 i lim (ma) notice that the i/v curve is uninterrupted when the power is shifted from the high-voltage battery to the low-voltage battery (if auxiliary battery option is used), if the transition occurs in the current-limit region of operation. this is shown in figure 24. vtip to gnd on hook (1/2)r dc begin current limiting (1/2)r dc (1/2)r dc + r lim decreasing loop length v bat i l v bat v oh C r l 2r p r dc ++ --------------------------------- = v bat v oh C () r l r l 2r p r dc ++ -------------------------------------------- 34 34 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for dc characteristics (continued) loop range the following equation is used to determine the dc loop range. where: r l = dc loop range. |v bat | = magnitude of battery voltage. v oh = slic overhead voltage. i l = dc loop current. r p = series protection resistor and resistance of l758x solid-state switch (if used). r dc = slic dc feed resistance. example 1, standard loop: calculate loop range with battery voltage of 48 v, slic maximum overhead of 7.8 v, slic dc feed resistance of 65 w , 18 ma loop current requirement, worst-case resistance of l758x switch of 28 w , and 50 w protec- tion resistor with worst-case 10% tolerance of 55 w . r l = 1937 w > 1800 w example 2, extended loop: with a C65 v battery voltage, assuming a slic nominal overhead of 7.1 v, slic dc feed resistance of 110 w , 18 ma loop current requirement, worst-case resistance of l758x switch of 28 w , and 50 w protection resistor with worst-case 10% tolerance of 55 w , what is the maximum loop length? dc applications on-hook transmission in order to drive an on-hook ac signal, the slic must set up the tip and ring voltage to a value less than the battery voltage. the amount that the open loop voltage is decreased relative to the battery is referred to as the overhead voltage. expressed as an equation, v oh = |v bat | C (v pt C v pr ) without this buffer voltage, amplifier saturation will occur and the signal will be clipped. the L8567 is auto- matically set at the factory to allow undistorted on-hook transmission of a 3.17 dbm signal into a 900 w ac loop impedance. the drive amplifiers are capable of 4 vrms minimum (v amp ). so, the maximum signal the device can guaran- tee is: the peak voltage at output of tip and ring amplifiers is related to the peak signal voltage by: 12-2563 (f) figure 27. slic 2-wire output stage r l v bat v oh C i l -------------------------------- 2 r p C r dc C = r l 48 v 7.8 v C 0.018 a ------------------------------------ 25528 + () () C 130 C = 2941 w 65 v 7.1 v C 0.018 a ------------------------------------ 25528 + () () C 110 C = v t/r 4 v z t/r z t/r 2r p + -------------------------- ? ?? = vamp = v t/r 1 2r p z t/r ----------- + ? ?? l l C v t/r [z t/r ]v amp + C r p r p + lucent technologies inc. 35 data sheet august 1999 peoples republic of china applications L8567 slic for dc applications (continued) on-hook transmission (continued) in addition to the required peak signal level, the slic needs about 2 v from each power supply to bias the amplifier circuitry. it can be thought of as an internal saturation voltage. combining the saturation voltage and the peak signal level, the required overhead can be expressed as: where v sat is the combined internal saturation voltage between the tip/ring amplifiers and v bat (4.0 v typical). r p ( w ) is the protection resistor value. z t/r ( w ) is the ac loop impedance. example: determine the required overhead to transmit on-hook (i loop = 0) a 3.17 dbm ac signal into a 900 w ac lead. assume use of 50 w protection resistors with a 10% tolerance or 55 w and an l7583 solid-state switch. the worst-case resistance of the switch is 28 w . note the minimum overhead voltage of the L8567 is 6.4 v. v on = 4.0 + 3.17 dbm = 20log vrms = 1.296 v v on = 4.0 + vrms = 1.296 v v on = 4.0 + v oh = 6.17 v < 6.4 v thus, an overhead of 6.17 v is needed for on-hook transmission of a 3.17 dbm signal into a 900 w ac load. the L8567 has a minimum overhead of 6.4 v. supervision both the loop closure and ring trip supervision func- tions are included on the L8567 slic. the outputs of these two supervision functions are internally wired- ored together to form a single output nstat. the wired-or connection of the loop supervision and ring trip detector is also available on pin nled. this pin has sufficient drive capability to drive an led. this pin is an open-collector output, so multiple pins can be used to drive a common led. also included is a slic thermal shutdown indicator, ntsd. note that the ring trip detector is not active in the low- power scan state. the ring trip detector must be active prior to applying power ringing to the subscriber loop. activate the ring trip detector by putting the L8567 slic into the powerup mode before applying power ringing to the subscriber loop. loop closure the on-hook to off-hook loop closure threshold is inter- nally set to a nominal 11 ma at v bat = C48 v. there is a nominal 2 ma hysteresis. this means that the off-hook to on-hook threshold will be a nominal 2 ma less than the on-hook to off-hook threshold. the loop closure threshold will track with battery voltage, increasing as the battery gets more negative. the loop closure com- parator has built-in longitudinal rejection, eliminating the need for an external 50 hz/60 hz filter. the loop closure detector is valid during scan, forward, and reverse active states. v oh v sat 1 2r p z t/r ----------- + ? ?? v t/r + = l 1 25528 + [] 900 --------------------------------- - + ? ?? 2v rms () v rms [] 2 900 ----------------------- - ? ?? 3 C 10 ----------------------------- 1 25528 + [] 900 --------------------------------- - + ? ?? 2v rms () 1 255 28 + [] 900 --------------------------- - + ? ?? 2 () 1.296 () 36 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for dc applications (continued) ring trip detection the ring trip circuit is a comparator that has a special input section optimized for this application. the equivalent circuit is shown in figure 28, along with its use in an application using unbalanced, battery-backed ringing. 12-3014 (f) figure 28. ring trip equivalent circuit and equivalent application + C r tsp r loop 15 k w 7 v i p = i n r tsn r ts2 2 m w 2 m w c rts1 0.022 f c rts2 0.27 f 274 k w phone hook rc phone v bat nrdet r ts1 402 w rtsp i n rtsn C + switch v ring the comparator input voltage compliance is v cc to v bat , and the maximum current is 240 a in either direction. its application is straightforward. a resistance (r tsn + r ts2 ) in series with the r tsn input establishes a current that is repeated in the r tsp input. a slightly lower resistance (r tsp ) is placed in series with the r tsp input. when ringing is being injected, no dc current flows through r ts1 , and so the r tsp input is at a lower potential than r tsn . when enough dc loop current flows, the r tsp input voltage increases to trip the com- parator. in figure 28, a low-pass filter with a double pole at 2 hz was implemented to prevent false ring trip. the following example illustrates how the detection cir- cuit of figure 28 will trip at 12.5 ma dc loop current using a C48 v battery. = 17.9 a the current i n is repeated as i p in the positive compar- ator input. the voltage at comparator input r tsp is: v rtsp = v bat + i loop(dc) x r ts1 + i p x r tsp using this equation and the values in the example, the voltage at input r tsp is C12 v during ringing injection (i loop(dc) = 0). input r tsp is, therefore, at a level of 5 v below r tsn . when enough dc loop current flows through r ts1 to raise its dc drop to 5 v, the comparator will trip. in this example, = 12.5 ma other supervision functions the L8567 has on-chip thermal shutdown circuitry. if the silicon die temperature exceeds a nominal 165 c temperature, the slic will sense this tempera- ture and enter the thermal shutdown mode, regardless of the logic inputs. the thermal shutdown mode is func- tionally similar to the disconnect state. when the die temperature cools, the slic will return to the reshut- down state. a hysteresis is included in the thermal shutdown mechanism. the L8567 also has a logic input pin, nextsd, whose status is transferred to the serial output data bus. this pin may be connected to an external monitoring device. an example is the thermal shutdown output pin of the l7583. if the l7583 enters the thermal shutdown mode, this is reflected in the tsd output pin of this device. the L8567 slic can accept this status pin and transfer the information on this pin to the serial output data bus. i n C7 v C (C48 v) 2.289 m w -------------------------------------- = i loop dc () 5 v 402 w ---------------- - = lucent technologies inc. 37 data sheet august 1999 peoples republic of china applications L8567 slic for dc applications (continued) latched parallel data interface the L8567 uses a latched parallel data control scheme for both logic inputs and logic outputs. there is a latch enable (en) pin associated with this control scheme. this data control scheme is designed to work in con- junction with the quad t7507 codec. the t7507 codec uses a serial data interface to receive and pass control information to and from the controlling processor. the t7507 controls the state of the L8567 slic via data inputs and outputs corresponding to those of the L8567 slic. the t7507 also provides the en control signal. the t7507 is a quad codec; that is, four channels in a single package. each quad codec is designed to con- trol the four corresponding L8567 slic devices. control inputs and outputs for the four channels are shared among the four slics. for example, there is only one b0 data output from the codec, and this control signal is passed to the b0 control input on the four associated slics. there are four en outputs from the codec, one to each slic. data on the shared input or output leads are valid to or from a given slic, depending on the state of en pin associated with the individual slic. this is shown in figure 29 below. the control data inputs to the slic are b0 and b1, which set the state of the slic and rd1i, rd2i, and rd3i, which control the state of the emr drivers. if an l7583 solid-state switch is used instead of emrs, the logic control outputs from the codec will go directly to the state control inputs of the switch. in this mode of operation, the relay drivers on the L8567 slic are not used. if this is the case, tie the logic inputs rd1i, rd2i, and rd3i to ground. this will force the drivers into the not-active state, which is the state with the lowest power consumption. for the slic logic inputs, the latch is controlled by input en. when en is high, the input data latches are active; that is, data at the b0, b1, rd1i, rd2i, and rd3i inputs are latched. the latched data will control the state of the slic and drivers, and the slic and drivers will not respond to changes at the logic inputs while the level at en is high. when en is low, the input data latch is not active; that is, data at the logic inputs will flow through the latch and immediately determine the state of the slic and drivers. logic outputs nstat and ntsd are also latched. there is an internal pull-up associated with each of these logic outputs. the operation of en with the logic outputs is slightly different from the operation of en with the logic inputs. in order for valid data to be at the nstat and ntsd outputs, both the internal detector (i.e., an off-hook or thermal shutdown condition, respectively, exists) and pin en must be low. table 24 explains this. 12-3457(f) figure 29. simplified control scheme L8567-0 en b0 nstat enable data input data output L8567-1 en b0 nstat L8567-2 en b0 nstat L8567-3 en b0 nstat en3 b0c nstatc en0 en1 en2 cclk d0 d1 csel clock data out data in chip select serial data interface to controller t7507 38 38 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for dc applications (continued) latched parallel data interface (continued) table 24. valid data at nstat and ntsd a simplified logic output latches schematic is shown in figure 30. 12-3455(f) figure 30. logic output latches like nstat, output nled also reflects loop closure and ring trip status. output nled is not latched. this output is an open-collector output with sufficient drive capabil- ity to drive an led. multiple nled can be connected to a common led. nled is valid regardless of the state of en. nled can be used as an unlatched alternative to nstat for control logic. ac design there are four key ac design parameters. termination impedance is the impedance looking into the 2-wire port of the line card. it is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. transmit gain is measured from the 2-wire port to the pcm highway, while receive gain is done from the pcm highway to the transmit port. finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. first-generation codecs these perform the basic filtering, a/d (transmit), d/a (receive), and -law/a-law companding. they all have an op amp in front of the a/d converter for transmit gain setting and hybrid balance (cancellation at the summing node). depending on the type, some have differential analog input stages, differential analog out- put stages, and -law/a-law selectability. this genera- tion of codecs is lower cost compared to second- and third-generation codecs, but needs the most compli- cated interface between the slic and codec. these codecs are most suitable for applications with fixed gains, termination impedance, and hybrid balance. second-generation codecs this class of devices includes a microprocessor inter- face for software control of the gains and hybrid bal- ance. the hybrid balance is included in the device. ac programmability adds application flexibility and saves several passive components and also adds several i/o latches that are needed in the application. however, there is no transmit op amp, since the transmit gain and hybrid balance are set internally. third-generation codecs this class of devices includes the gains, termination impedance, and hybrid balanceall under micropro- cessor control. depending on the device, it may or may not include latches. this generation of codec offers a very simple slic-codec interface with a minimal num- ber of external components. t7507 codec the t7507 provides third-generation codec functional- ity without the programmability. in the t7507, ac gain, termination impedance, and the hybrid balance net- work are set digitally; thus, the slic-codec interface requires virtually no external components. however, because all the ac parameters are fixed (and set for requirements in the prc), the device is an extremely cost-effective solution. en state nstat 0 off-hookloop closure or ring trip 0 0 on-hook 1 1dont care 1 en state ntsd 0 device in thermal shutdown 0 0 normal operationdevice state deter- mined by b0, b1, and rd1 inputs 1 1dont care 1 nrdet nlc nstat en control internal loop closure detectors lucent technologies inc. 39 data sheet august 1999 peoples republic of china applications L8567 slic for outline diagrams 32-pin plcc dimensions shown are metric. note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schemat- ics to assist your design efforts, please contact your lucent technologies sales representative. 5-3813 (f)r01 0.10 seating plane 0.38 min typ 1.27 typ 0.330/0.533 1 430 5 13 21 29 14 20 12.446 0.127 11.430 0.076 pin #1 identifier zone 14.986 0.127 13.970 0.076 3.175/3.556 40 lucent technologies inc. data sheet august 1999 peoples republic of china applications L8567 slic for outline diagrams (continued) 44-pin plcc dimensions shown are metric. note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schemat- ics to assist your design efforts, please contact your lucent technologies sales representative. 5-2506 (f) r07 4.57 max 1.27 typ 0.53 max 0.10 seating plane 0.51 min typ 1 640 7 17 29 39 18 28 pin #1 identifier zone 16.66 max 17.65 max 16.66 max 17.65 max lucent technologies inc. 41 data sheet august 1999 peoples republic of china applications L8567 slic for ordering information device part no. description package comcode lucL8567aau-d prc slic 32-pin plcc (dry-bagged, tube) 107891236 lucL8567aau-dt prc slic 32-pin plcc (dry-bagged, tape and reel) 107891244 lucL8567ap-d prc slic 44-pin plcc (dry-bagged, tube) 107957706 lucL8567ap-dt prc slic 44-pin plcc (dry-bagged, tape and reel) 107957714 l u cent t echn o logies i n c. re s e r v es t h e r i g ht t o ma k e chan g es to t he p r oduct ( s) o r in f o r m ation c o ntain e d he r ein with o ut no t i c e . n o liability i s assum e d as a res u l t of t h eir us e or applicatio n . no rights u nde r a n y pa t ent acc o mpa n y the s a l e of a n y such p r oduct ( s) o r in f o r m a tion. co p yright ? 199 9 luce n t t ec h nologie s inc. all rights res e r v ed a ugust 19 9 9 ds99 - 100alc (replaces d s 98-001 a lc) f o r a d d i ti o n a l i n fo r m a t i o n , c o n ta c t y o u r m i c r o e l e c t r o n i c s g r o u p a cc o u n t m a n a ge r o r t h e f o l l o wi n g: i n terne t : http://ww w . lucent.com/mic r o e-m a il: do c m a ste r @mi c r o .lu c ent. c om n. a m erica : microelectronics grou p , lucent t echnologies i nc., 555 union boul e v ard, room 30l-15 p -ba, allent o wn , p a 18103 1 - 80 0 - 37 2 - 2 4 4 7 , f a x 6 10 -7 1 2 - 4 1 06 ( i n c an a d a: 1 - 8 0 0 - 5 5 3 - 2 44 8 , f a x 6 1 0 - 71 2 - 4 1 06) asia p a cif i c : microelectronics grou p , lucent t echnologies singapore pt e . l t d. , 77 s cience p a r k d r i v e , #03-18 cintech iii , singa p o r e 1 1 82 5 6 t el. ( 65 ) 7 7 8 8 8 33 , f a x ( 6 5 ) 7 7 7 74 9 5 c h i n a: m i c r o e l e c t r o n i cs g r o u p , l u c e n t t e c hn o l o g i e s ( c h i na ) c o ., lt d ., a- f2 , 2 3 / f , za o f o n g u n i v e r s e b u i l d i n g , 18 0 0 zho n g s h a n x i r o a d , s h a ng h a i 2 00 2 3 3 p . r. c h i na t el. ( 86 ) 21 64 4 0 0 4 6 8 , ext . 316 , f a x ( 86 ) 21 64 4 0 0 6 5 2 j a p a n: m i c r o e l e c t r o n i cs g r o u p , l u c e n t t e c h n o l og i e s j ap a n l t d ., 7 - 1 8 , h i ga s h i - g o ta n d a 2 -c h o m e , s h i n a g a w a - k u , t o k y o 1 4 1, j a p an t el. ( 81 ) 3 5 42 1 1 6 0 0 , f a x ( 8 1 ) 3 5 4 2 1 17 0 0 e u r o p e : d at a r e qu e s t s : m ic r o e l e c t r o n ic s g r ou p d a t a li n e : t e l. ( 4 4 ) 7 00 0 5 8 2 36 8 , f a x ( 4 4 ) 1 1 8 9 3 2 8 148 t e c h n i cal i n q u i r i e s : ge r ma n y : ( 4 9 ) 8 9 9 50 8 6 0 (m u n i c h ) , u n i t e d ki n gdo m : ( 4 4 ) 1 3 44 86 5 9 0 0 (ascot), f r a n ce : ( 3 3 ) 1 4 0 8 3 6 8 0 0 (p a r i s), s we d e n : ( 4 6) 8 5 9 4 6 07 00 (sto c k h o l m) , fi n land : ( 3 5 8 ) 9 4 3 54 28 0 0 (h e ls i n k i), i t a l y : ( 3 9 ) 0 2 6 6 0 8 13 1 (m i l a n), s p ai n : ( 3 4 ) 1 8 0 7 1 4 4 1 (mad r id) |
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